DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 133

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.1.3 PCI Bus Arbitration
The PCI bus can be arbitrated as shown in
PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been
granted, the initiator waits until both PIRDY and PFRAME are deasserted (i.e., an idle cycle) before
acquiring the bus and beginning the transaction. As shown in
when it was granted and the device had to wait until clock cycle #6 before it acquired the bus and began
the transaction. The arbiter can deassert PGNT at any time and the initiator must relinquish the bus after
the current transfer is complete, which can be limited by the latency timer.
Figure 10-4. PCI Bus Arbitration Signaling Protocol
10.1.4
If a target fails to respond to an initiator by asserting PDEVSEL and PTRDY within 5 clock cycles, then
the initiator aborts the transaction by deasserting PFRAME and then, one clock later, by deasserting
PIDRY
PCI command/status configuration register (Section 10.2).
Figure 10-5. PCI Initiator Abort
(Figure
PCLK
PREQ
PGNT
PFRAME
PCLK
PFRAME
PIRDY
PTRDY
PDEVSEL
PCI Initiator Abort
10-5). If such a scenario occurs, it is reported through the master abort status bit in the
1
1
Wait for PGNT Asserted
and then PFRAME and
PIRDY Deasserted
2
2
3
3
4
4
Figure
133 of 183
5
5
10-4. The initiator requests bus access by asserting
6
6
Bus is Acquired
Figure
7
7
10-3, the bus was still being used
8
8
9
9
Bus is Relinquished
10
10