DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 33

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive
DMA does not pass any data from the receive FIFO to the PCI bus, even if one or more HDLC channels is
enabled. On device initialization, the host should fully configure the receive DMA before enabling it through this
bit.
Bit 1/Receive DMA Throttle Select Bit 0 (RDT0); Bit 2/Receive DMA Throttle Select Bit 1 (RDT1). These
two bits select the maximum burst length that the receive DMA is allowed on the PCI bus. The DMA can be
restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256
dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system
environment for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency
and bus efficiency.
Bit 3/Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to 0, the
transmit DMA does not pass any data from the PCI bus to the transmit FIFO, even if one or more HDLC channels
is enabled. On device initialization, the host should fully configure the transmit DMA before enabling it through
this bit.
Bit 4/Transmit DMA Throttle Select Bit 0 (TDT0); Bit 5/Transmit DMA Throttle Select Bit 1 (TDT1). These
two bits select the maximum burst length the transmit DMA is allowed on the PCI bus. The DMA can be restricted
to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords
(1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment
for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency and bus
efficiency.
Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either
Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest
address, while Big Endian places the least significant byte at the highest address. This bit setting only affects
HDLC data on the PCI bus. All other PCI bus transactions to the internal device configuration registers, PCI
configuration registers, and local bus are always in Little Endian format.
0 = receive DMA is disabled
1 = receive DMA is enabled
00 = burst length maximum is 32 dwords
01 = burst length maximum is 64 dwords
10 = burst length maximum is 128 dwords
11 = burst length maximum is 256 dwords
0 = transmit DMA is disabled
1 = transmit DMA is enabled
00 = burst length maximum is 32 dwords
01 = burst length maximum is 64 dwords
10 = burst length maximum is 128 dwords
11 = burst length maximum is 256 dwords
0 = HDLC packet data on the PCI bus is in Little Endian format
1 = HDLC packet data on the PCI bus is in Big Endian format
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