DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 34

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bits 7 to 11/BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These bits select which port has the dedicated
resources of the BERT.
00000 = Port 0
00001 = Port 1
00010 = Port 2
00011 = Port 3
00100 = Port 4
00101 = Port 5
00110 = Port 6
00111 = Port 7
Bit 12/Receive FIFO Priority Control Bit 0 (RFPC0); Bit 13/Receive FIFO Priority Control Bit 1 (RFPC1).
These bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest priority to the
DMA to transfer data from the FIFO to the PCI bus. In the priority decoded scheme, the lower the HDLC channel
numbers, generally the higher the priority. In schemes ’10 and ’11, the upper priority decode channels have
priority over the lower priority decode channels.
Bit 14/Transmit FIFO Priority Control Bit 0 (TFPC0); Bit 15/Transmit FIFO Priority Control Bit 1
(TFPC1). These two bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest
priority to the DMA to transfer data from the PCI bus to the FIFO. In the schemes ’01 and ‘11m upper priority
decode channels have priority over the lower priority decode channels.
5.3 Status and Interrupt
5.3.1 General Description of Operation
There are three status registers in the device: status master (SM), status for the receive V.54 loopback
detector (SV54), and status for DMA (SDMA). These registers report events in real-time by setting a bit
within the register to 1. All bits that have been set within the register are cleared when the register is
read, and the bit is not set again until the event has occurred again. Each bit can generate an interrupt at
the PCI bus through the PINTA output signal pin, and, if the local bus is in the configuration mode, then
an interrupt also be created at the LINT output signal pin. Each status register has an associated interrupt
mask register, which can allow/deny interrupts from being generated on a bit-by-bit basis. All status
registers remain active even if the associated interrupt is disabled.
SM Register
The status master (SM) register reports events that occur at the port interface, at the BERT receiver, at
the PCI bus, and at the local bus. See
The port interface reports change-of-frame alignment (COFA) events. If the software detects that one of
these bits is set, the software must begin polling the RP[n]CR or TP[n]CR registers of each active port (a
maximum of 16 reads) to determine which port or ports has incurred a COFA. Also, the host can
allow/deny the COFA indications to be passed to the SRCOFA and STCOFA status bits through the
00 = all HDLC channels are serviced round robin
01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin
10 = HDLC channels 16 to 1 are priority decoded; HDLC channels 17-up are round robin
11 = HDLC channels 64 to 1 are priority decoded; HDLC channels 65-up are round robin
00 = all HDLC channels are serviced round robin
01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin
10 = HDLC channels 16 to 1 are priority decoded; other HDLC channels 17-up re round robin
11 = HDLC channels 64 to 1 are priority decoded; other HDLC channels 65-up are round robin
01000 = Port 8
01001 = Port 9
01010 = Port 10
01011 = Port 11
01100 = Port 12
01101 = Port 13
01110 = Port 14
01111 = Port 15
Figure 5-1
10000 = Port 0 (high speed)
10001 = Port 1 (high speed)
10010 = Port 2 (high speed)
10011 = n/a
10100 = n/a
10101 = n/a
10110 = n/a
10111 = n/a
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for details.
11000 = n/a
11001 = n/a
11010 = n/a
11011 = n/a
11100 = n/a
11101 = n/a
11110 = n/a
11111 = n/a