DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 77

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive
starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently
presetn in the RFSBP register and write it to the channel location indicated by the HCID bits. When the device
completes the write, the IAB is set to 0.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation completes.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 9/Starting Block Pointer (RSBP0 to RSBP9). These bits determine which of the 1024 blocks within the
receive FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of
the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits
are read, they report the current block pointer being used to write data into the receive FIFO from the HDLC Layer
2 engines.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 9/Block ID (BLKID0 to BLKID9)
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive block
pointer RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the block
location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be
read from the RFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal receive
0000000000 (000h) = use block 0 as the starting block
0111111111 (1FFh) = use block 511 as the starting block
1111111111 (3FFh) = use block 1023 as the starting block
0000000000 (000h) = block number 0
0111111111 (1FFh) = block number 511
1111111111 (3FFh) = block number 1023
BLKID7
RSBP7
IAB
n/a
15
15
7
7
0
0
RFSBP
Receive FIFO Starting Block Pointer
0904h
RFBPIS
Receive FIFO Block Pointer Indirect Select
0910h
BLKID6
RSBP6
IARW
n/a
14
14
6
6
0
0
BLKID5
RSBP5
n/a
n/a
13
13
5
5
0
0
BLKID4
RSBP4
n/a
n/a
12
12
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4
4
0
0
BLKID3
RSBP3
n/a
n/a
11
11
3
3
0
0
BLKID2
RSBP2
n/a
n/a
10
10
2
2
0
0
BLKID1
BLKID9
RSBP1
RSBP9
1
9
1
0
9
0
BLKID0
BLKID8
RSBP0
RSBP8
0
8
0
0
8
0