DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 24

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Signal Name:
Signal Description:
Signal Type:
The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device
is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this
signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PSTOP is tri-stated.
Signal Name:
Signal Description:
Signal Type:
This input signal is used as a chip select during configuration read and write transactions. This signal is disabled
when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase
of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device
allows access to the PCI configuration registers, and the PDEVSEL signal is asserted during the PCLK cycle.
PIDSEL is sampled on the rising edge of PCLK.
Signal Name:
Signal Description:
Signal Type:
The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to
indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK
cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an
output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is
sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PDEVSEL is tri-stated.
Signal Name:
Signal Description:
Signal Type:
The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is
updated on the rising edge of PCLK.
Signal Name:
Signal Description:
Signal Type:
The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus
has been granted. The device samples PGNT on the rising edge of PCLK and, if detected, initiates a bus
transaction when it has sensed that the PFRAME signal has been deasserted.
Signal Name:
Signal Description:
Signal Type:
This active-low signal reports parity errors. PPERR can be enabled and disabled through the PCI configuration
registers. This signal is updated on the rising edge of PCLK.
Signal Name:
Signal Description:
Signal Type:
This active-low signal reports any parity errors that occur during the address phase. PSERR can be enabled and
disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.
PSTOP
PCI Stop
Input/Output (tri-state capable)
PIDSEL
PCI Initialization Device Select
Input
PDEVSEL
PCI Device Select
Input/Output (tri-state capable)
PREQ
PCI Bus Request
Output (tri-state capable)
PGNT
PCI Bus Grant
Input
PPERR
PCI Parity Error
Input/Output (tri-state capable)
PSERR
PCI System Error
Output (open drain)
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