XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 7

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XS1-L02A-QF124-I5

Manufacturer Part Number
XS1-L02A-QF124-I5
Description
IC MPU 32BIT DUAL CORE 124QFN
Manufacturer
XMOS

Specifications of XS1-L02A-QF124-I5

Processor Type
XCore 32-Bit
Speed
500MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
124-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1031
XMOS
Figure 1 Summary: tokens transferred for ordinary and configuration data. Control
tokens are white on black.
3.1 Physical layer
LLink communication uses a transition-based non return-to-zero signalling scheme.
Bits are sent at a rate derived from the XS1 clock; this rate can be programmed
to meet applications requirements. All links have a weak pull down, but an ex-
XS1-L S
YSTEM
Sending ordinary data
Channel layer
Dreg
Message
Sent to switch and over links
Message
Sent to processor NodeID on switch NodeID
Message
Seen on channel ChID on node NodeID
Message
Sending configuration data
Channel layer
Dreg
Message
Sent to switch and over links
Message
S
PECIFICATION
ChID
ChID
Cwr
Node ID ChID 2
Node ID ChID
Node ID ChID
Node ID
Node ID
First part of mess
First part of mess
First part of mess
Another part of mess
Reply channel,
address & data
SSctl
PSctl 12
(0.9)
SSctl
PSctl
Cwr
Cwr
First part of mess
Another part of mess
Pse
Reply channel,
address & data
Another part of mess
Eom
Pse
Another part of mess
Eom
Pse
Eom
Eom
Eom
Eom
2008/08/25
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