XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 38

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
9.2 Processor switch registers (per core)
The following registers are in the processor switch. They can be accessed over
JTAG or by sending a message to the processor switch. The message to be
sent is specified in Section 3.6.2. These registers are specific to a processor.
XS1-L S
Address
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x10-0x13
0x40-0x47
0x60-0x67
0x80-0x9F
0x20-0x27
YSTEM
S
Contents
Device ID register
Number of resources - I
Number of resources - II
Control PSwitch permissions to debug registsers.
Debug interrupts
Processor clock divider (only lower 16 bits are used)
Value of the OTP security register bits 0..31, see Section
Internal link status Internal LinkPA, PB, PC PD, see Section 9.4. Ver-
ification only.
Scratch register for debug software protocols 0-7
Copy of the PC of threads 0-7
Copy of the SR of threads 0-7
LLink status of LLINK 0-31, see Section 9.4. Verification only.
PECIFICATION
bits 7..0: XCore version, 0x0
bits 15..8: XCore revision, 0x3
bits 31..16: Node/Core number, taken from SSWitch
bits 7..0: Number of Threads
bits 15..8: Number of Synchronisers
bits 23..16: Number of Locks
bits 31..24: Number of Channel Ends
bits 7..0: Number of Timers
bits 15..8: Number of Clock Blocks
bit 0: Disable write access to processor registers.
bit 8: Disable remote access, can only be cleared locally.
bit 31: Disable further updates to any PSwitch register
bit 0: Writing a 1 generates a debug interrupt.
(0.9)
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