XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 17

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
16/40
number of the first bit that differs specifies the dimension (direction) in which the
message needs to be routed; this results in eight possible routing dimensions.
The routing table associates each outgoing link with exactly one dimension, and
the switch picks an available outgoing link for this dimension before forwarding
the stream. This mechanism enables system designers to construct the routing
tables for meshes, pipelines or hypercubes.
The node identifier of the XS1-L is initialised by writing its value in 15 ... 0 of the
node identifier register. The most significant 16 bits are ignored.
Each link can be associated with one of four logical networks by writing the
network number to bits 5 ... 4 of the link’s configuration register. These network
numbers correspond to the network numbers used when initialising channels
using the SETN instruction.
A 16-entry look-up table associates a mismatch in each of the 16 node address
bits with a logical direction. Each entry in this look-up table is large enough
to hold an outgoing logical direction. Assuming that there are no more than
16 directions, this lookup-table logically comprises 64 bits; since there are only
eight LLinks on a XS1-L only 48 bits need to be present.
The table is accessible via the configuration registers at addresses 0xC and 0xD
in the system switch. The least significant four bits on address 0xC hold the
direction for node address bit 0, the most significant four bits on address 0xD
hold the direction for node address bit 15. Note that it is likely that multiple
copies of this look-up table will be needed to eliminate routing latency arising
from access contention.
Each LLink can be associated with one of the directions by writing the direction
to bits 10 ... 7 of the LLink’s configuration register. Four bits are sufficient for up
to 16 directions. On the XS1-L only 3 bits are used.
NOTE: The node address is received most significant bit first, so direction 15 is
selected if the first bit received does not match bit 15 of the node address.
Two example topologies are shown below; a regular pipeline Figure
2
shows
a regular pipeline and Figure
3
shows a mesh with missing wires (or pipe of
pipelines). Other examples (such as hypercubes, trees, meshes, tori, and com-
binations of those) are easily constructed. Each node shows the node-id, the
direction associated with each link, and the direction associated with each mis-
matching address bit.
XS1-L S
S
(0.9)
2008/08/25
YSTEM
PECIFICATION