XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 3

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
The CRC is calculated over the byte stream represented by the program size and
the program itself. The polynomial used is 0xEDB88320 (IEEE 802.3); the CRC
register is initialised with 0xFFFFFFFF and the residue is inverted to produce
the CRC.
The CRC check can be disabled by setting the CRC to 0x0D15AB1E.
2.2 Boot from SPI interface
To boot from an SPI interface, an SPI slave device must be connected as follows.
A READ command is issued with a 24-bit address 0x000000. Based on the 100
MHz reference clock of the XCore, an SPI clock rate of 2.5 MHz is used. The
clock polarity / phase is of 0 / 0.
The XCore expects each byte to be transferred with the least-significant bit first.
Many programmers write bytes into an SPI interface using the most significant
bit first, so you may have to reverse the bits in each byte of the image stored in
the SPI device.
If a large boot image is to be read in, it is faster to first load a small boot-loader
that reads the large image using a faster SPI clock, for example 50 MHz or as
fast as the flash device supports.
If field-upgradeable firmware is required, a small boot-loader should be stored in
the first sector of flash memory, followed by two boot-images starting on sector
boundaries. The boot-loader should be written to read the first image initially,
and on CRC failure boot from the second image. On upgrade, the first image
XS1-L S
Port
P1A0
P1B0
P1C0
P1D0
1. The program size s in words - a 32-bit value, least significant byte first.
2. Program consisting of s
3. A 32-bit CRC, least significant byte first.
YSTEM
Use
SPI MISO
SPI SS
SPI SCLK
SPI MOSI
S
PECIFICATION
(0.9)
4 bytes.
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