XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 20

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
3.4 Arbitration
The arbitration should be fair, and should give fair bandwidth to all input links
and load-balance all output links.
3.5 Processor communication
When processors communicate with each other, they transmit messages over
the switches that, in addition to the 16- or 3-bit switch header include an 8- or
5-bit channel-end identifier. When a message is transmitted to the switch, it has
a 24-bit (16 bits core-id + 8 bits channel-end) or 8-bit (3 bits core-id + 5 bits
channel-end) header. When a message is transmitted to the processor over
an internal link, the message always has an 8-bit header which indicates the
channel-end. If 1-byte switch headers is used, the first three bits of this byte will
always be 0.
Processors can also communicate with switches. In this case the switch must be
set to 3-byte header mode. When a message is transmitted to the switch, it con-
tains a 2-byte header, and then a control token PSCTRL or SSCTRL (CHECK!!!).
This indicates that the message is destined for the processor-control or switch-
control associated with the processor addressed by the first two bytes. Mes-
sages that are transmitted to the PSCTRL or SSCTRL follow the following for-
mat:
XS1-L S
• Two byte header identifying the destination processor/switch
• PSCTRL or SSCTRL token
• WRITEC control token
• Two bytes identifying core that reply should go to
• One byte identifying Channel-end for reply
• Two bytes identifying address within switch (address[15 ... 8], address[7 ... 0])
• Four bytes data to be written (data[31 ... 24], data[23 ... 16], data[15 ... 8],
• END control token (value (0x01)
data[7 ... 0])
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