XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 34

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
8 Secure boot module
The security module comprsises two parts: a configuration register (32 bits), and
a one time programmable memory to store program code. The security register
has the following layout:
The memory itself comprises four sectors containing 2KBytes each. The banks
are organised contiguously and can be used as a single 8KByte bank, but each
sector can be locked independently if required.
The OTP memory is programmed using three special I/O ports: the OTP address
port is a 16-bit port with resource ID 0x100002XX, the OTP data is written via
a 32-bit port with resource ID 0x200001XX, and the OTP control is on a 16-bit
port with ID 0x100003XX.
[to be provided - guide to programming the OTP]
XS1-L S
Bits
0
1
2
3
5
8
9
10
11
12
13
14
21..15
31..22
YSTEM
Meaning
Disable JTAG debug access to this core
Disable access to Processor Control registers over the
switch; all reads of any pswitch register return 0, writes are
ignored
Disable DFT scan chains into this core
Disable DFT scan chains for the top level of chip
Force boot from address 0x000 of OTP, ignore the boot con-
figuration register
Disable programming of OTP sector 0
Disable programming of OTP sector 1
Disable programming of OTP sector 2
Disable programming of OTP sector 3
Disable OTP programming completely: disables updates to
all sectors and the security register
Disable all (read & write) access from the JTAG interface to
this OTP
Disable any interaction with GlobalDebug for this XCore
General purpose software accessable security register
available to end-users
Core 0 - general purpose user programmable JTAG UserID
code extension; Cores 1, 2, and 3 - general purpose avail-
able to end-users
S
PECIFICATION
(0.9)
2008/08/25
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