XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 40

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
9.4 Link status/control bit formats
The LLinkand internal link registers have the following structure - where the Di-
rection bits are 0 for internal links and LLinks.
XS1-L S
Address
0x10
0x1F
0x20-0x27
0x40-0x43
0x80-0x87
0xA0-0xA7
bits
0
1
2
5..4
11..8
23..16
25..24
YSTEM
use
SRC INUSE
DST INUSE
JUNK
Network - a network ID can be written in those bits
the direction to which this link belongs
SRC TARGET ID
SRC TARGET TYPE
S
Contents
GlobalDebug configuration for XCore0
bit 0: Drive the global debug pin on global debug events
bit 1: Allow the global debug pin to generate global debug events
global debug source.
bit 0: Set if XCore0 is the source of the last global debug event
bit 4: Set if the global debug pin is the source of the last global debug
event
LLink 0-7 direction and network, see Section
Internal link 0-4 network, see Section
LLink 0-7 speed, timing, and width
bit 10 ... 0: minimum number of system clock cycles between tokens
bit 21 ... 11: minimum number of system clock cycles between sym-
bols
bit 23: RESET input state machine
bit 24: Issue a HELLO and clear credits-counter
bit 25: RO Link has credits and can transmit
bit 26: RO Link has issued credits and can receive
bit 27: RO (cleared by reading), Link protocol error.
bit 30: Number of signal wires - 0: two pairs; 1: five pairs
bit 31: Enable link
LLink 0-7 static forwarding header
bit 7 ... 0: Channel end
bit 15 ... 8: Core identifier (0 on XS1-L)
bit 31: enable static forwarding
PECIFICATION
(0.9)
9.4
9.4
2008/08/25
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