XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 39

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
9.3 Interconnect registers (per node)
The following registers are in the interconnect - they can be accessed over JTAG
or by sending a message to the system switch. The message is specified in
Section 3.6.2. Changing these registers has a global effect on the chip.
XS1-L S
Address
0x01
0x04
0x05
0x06
0x07
0x08
0x0C
0x0D
0x00
YSTEM
S
Contents
Device identification
Number of resources
Node configuration
Node ID, lower 16 bits only
PLL control register.
Lowest 16 bits set the switch clock frequency, clk = pll (n + 1). Keep
at 0 for 400 MHz.
Lowest 16 bits define the relation between the reference clock and
the PLL clock, ref = pll (n + 1). Keep at 3 for 100 MHz.
Directions for bits 0 to 7
bits 3..0: Direction for bit 0
bits 7..4: Direction for bit 1
...
bits 31..28: Direction for bit 7
bits 3..0: Direction for bit 8
bits 7..4: Direction for bit 9
...
bits 31..28: Direction for bit 15
PECIFICATION
bits 7..0: SSwitch version, 0x1
bits 15..8: SSwitch revision, 0x0
bits 23..16: The value of the SS MODE pins, sampled on reset
bits 7..0: Number of internal links per core
bits 15..8: Number of Cores
bits 23..16: Number of LLinks
bit 0: Short headers (use 1-byte headers if set)
bit 8: Disable PLL modifications.
bit 31: Disable further updates to any SSwitch control register.
bit 5..0: PLL reference divider: R
bit 20..8: PLL feedback divider: F
bit 25..23: PLL output divider: OD
(0.9)
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