XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 12

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
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tokens. The addresses and contents of the speed registers are summarised in
Section 9.3.
On a system-reset the link is set to a serial LLink mode using two pairs. This
enables boot over LLinkto work. The number of clock cycles spacing tokens
should be reset to 400 and the number of clock cycles between symbols should
be set to 400.
The speed of an LLink is adjusted by changing the number of clock cycles be-
tween tokens and the number of clock cycles between symbols. Generally, these
are both set to the same value. The token spacing field is encoded with an offset
of 2, ie, 0x000 represents 2 cycles delay, 0x001 represents 3 cycles delay, up
to 0x7ff representing 2049 cycles delay. The symbol spacing field is encoded
with an offset of 1, ie, 0x000 represents a single cycle delay, 0x001 represents a
two-cycle delay, etc and 0x7ff represents a 2048 cycle delay. The XS1-L cannot
receive data if the transmitter does not space the symbols by at least two clock
cycles. All clock cycles are relative to the switch clock, which clocks at 400 MHz
by default, but can be set to run slower using register 7 (see Section 9.3).
For a 400 MHz system clock and bit spacing s
2, the data rate achievable
using 2 signal wires is (160 s) Mbits/second; the data rate using 5 signal wires
is (400 s) Mbits/second. The actual speed that can be achieved depends on the
electrical characteristics of the physical connection. Note that the XS1-L cannot
receive bits faster than half the switch clock rate. When two XS1-Ls are running
at the same clock, they should set their inter symbol delay to at least 2. If one of
the XS1-Ls has a lower switch-clock-speed, the other one should adjust its inter
symbol rate accordingly.
3.2 Link layer
The link layer protocol operates a point-to-point connection over a full-duplex
LLink. The link layer governs when data is transmitted, and how links start
communicating. Four control tokens are used by the link layer: CREDIT8,
CREDIT16, CREDIT64, and HELLO.
A link can be disabled or enabled. When disabled, no outside signals are coming
through to the link state machine. When enabled, signals come through and are
assembled into tokens.
When asked to transmit a HELLO, the LLink resets its credits counter, and trans-
XS1-L S
S
(0.9)
2008/08/25
YSTEM
PECIFICATION