XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 25

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
To read data, the following sequence is sent:
This results in the following reply message:
All messages for SSCTRL must be sent on network 0, and all responses will
be on network 0 too. SSCTRL messages must not be sent from other network
numbers.
3.6.3 Configuring channel ends
Channel ends are configured using the SETD instruction. The SETD instruction
takes a 32-bit resource-id. This resource-id must be either another channel end
(type 2), a configuration channel (type 12), or a null-channel (type ???). The
least significant 8 bits are the resouce type, the following 8 bits the number of
the channel-end (or in the case of a configuration special valus 0xc2 or 0xc3 to
indicate whether to control PSCTRL or SSCTRL), and the most significant 16
bits are the core and processor identifier.
XS1-L S
• READC control token (value 0xC1)
• Return channel end identifier (Node, Processor, Channel-end)
• Address within switch (address[15 ... 8], address[7 ... 0])
• END control token (value (0x01)
• ACK control token (value 0x03)
• Data read (data[31 ... 24], data[23 ... 16], data[15 ... 8], data[7 ... 0])
• END control token (value 0x01)
OUTT
OUTT
OUT
OUTCTI r5, 1
CHKCTI r5, 3
CHKCTI r5, 1
FREER
YSTEM
S
r5, r11
r5, r2
r5, r3
r5
PECIFICATION
(0.9)
// high 16 bits of reg value: 0
// low 16 bit of reg address, from r2
// value to be stored in r3
// in token
// check for ACK packet coming back
// termination of ACK packet
// release channel end
2008/08/25
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