XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 31

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
NOTE: The registers can only be written by this XCore. If other cores need to
control the power-state of this processor, they need to activate a local thread.
It is recommended that user code tests the wakeup condition immediately before
issuing the sleep signal.
A potential race condition exists between the internal assertion of sleep and the
external assertion of SS ENABLE. The race is between the test of the wakeup
(or ’work available’) condition by the instruction set (’ISA Test’) and the test of
the SS ENABLE (external wakeup signal) from the FSM (’SS ENABLE Test’). If
the SS ENABLE pulse is swallowed between these two points, the device will
not wake up.
This is complicated by the fact that these two endpoints exist in different clock
domains and the duration of the period between the ISA Test and the assertion
of the sleep signal is determined by the number of instructions specified or im-
plied by the user. In the case where the assertion of sleep and SS ENABLE are
co-incident, both signals must be synchronised into the FSM clock domain (2
cycles), the FSM state must then transition into the sleep state (1 cycle). The
wakeup condition must still be valid in this state to ensure that it is not missed.
It is recommended that the pulse width of SS ENABLE is a minimum of two
SS CLK cycles plus the additional cycles to accomodate the core clock resyn-
chronisation of the external wakeup condition signal and the user instructions
between ISA test and the assertion of sleep.
XS1-L S
Current
state
Sleep (S)
Energise (E)
Active (A)
YSTEM
SS RESETB SS ENABLE SLEEP dec.zero core VDD OK Next state SS VDD GATE
inactive
inactive
inactive
inactive
active
active
active
S
PECIFICATION
active
X
X
X
X
X
X
Inputs
active
X
X
X
X
X
X
(0.9)
active
X
X
X
X
X
X
X
X
X
X
X
X
X
A
E
E
A
E
A
S
0
High-Z
High-Z
Outputs
active
inactive
inactive
dec. enable
2008/08/25
CORE RESETB
active
active
inactive
30/40