XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 5

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
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2.4 Boot from Security Module
If a core is set to use secure boot, the program in boot format is taken from
address 0 of the OTP memory in the core’s security module. Each core has its
own individual OTP memory, and hence some cores can be booted from OTP
while others are booted from SPI or the channel interface. This enables an 1L to
be partially programmed, dedicating one or more cores to perform a particular
function, leaving the other cores user-programmable.
3 LLink specification
The interconnect provides communication between all tiles on the system. A
system can comprise one or more nodes, that may be physically separated. In
conjunction with simple programs, the interconnect can also be used to support
access to the memory on any tile from any other tile, and to allow any tile to
initiate programs on any other tile.
The interconnect allows streams of data to be communicated with low latency. A
stream comprises data tokens and control tokens, where data tokens contain 8
bits of data, and control tokens specify operations. Streams are circuit switched,
but they can be set-up and terminated at low cost. This enables the network to
be used as a packet switching network, where short packets are carried through
the interconnect in a pipelined manner.
Each tile has four links that connect the tile to an on-chip switch that provides
non-blocking communication between the tiles on a node. The on-chip switch
also provides a number off-chip LLinks that can be connected to LLinks of other
nodes. The structure and performance of the LLink connections can be varied
to meet the needs of applications. The topology of the interconnect is not fixed,
a topology appropriate to the application can be used.
The network supports partitioning. For example, partitioning provides separation
between data intensive streams and control streams. Partitioning provides real
time guarantees for parts of the network that need the guarantees.
As far as a program is concerned, communication always takes place between
two channel ends. A channel end is a physical resource that is allocated on the
XCore ˙ Channels-ends reside on a tile and are identified by means of an identifier
on the tile, a tile-identifier, and a node-identifier. Data is transmitted to a channel
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PECIFICATION