XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 36

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
9.1 Processor status registers
The following are processor status registers that are accessed using GETPS
and SETPS. The regsiter number must be translated to a resource ID by shifting
the register number left 8 bits, and oring 0x0B in (the resource ID that identifies
a processor control register).
XS1-L S
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
YSTEM
PS RAM BASE
PS VECTOR BASE
PS XCORE CTRL0
S
PECIFICATION
(0.9)
RW Address of RAM. Keep at 0x00010000.
RW Base of all 0 resource vectors. Used for both
RW General control
RO
Contents
events and interrupts. Bits 31-16 should be
set, bits 15-0 should be kept 0.
Value of the boot mode pins
Reserved
Value of the OTP security register bits 0..31,
see Section
WO Oscillator control register
bits 15..0: RO Value of counter CoCl
bits 15..0: RO Value of counter CoWi
bits 15..0: RO Value of counter PeCl
bits 15..0: RO Value of counter PeWi
Power control wake-up counter.
Power control wake-up. Bit 0 indicates “go to
sleep”
bit 0: (verif) Reference clock from core clock
bit 4: enable divider
bit 5: enable divider only on WAIT
bit 0: enable oscillator PeCl, PeWi
bit 1: enable oscillator CoCl, CoWi
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