XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 2

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
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1 Introduction
This document specifies the XS1-L boot protocol, link specification, switch spec-
ification and token specifications. It is related to the L1, L2, and L4 processors
which are single, dual, and quad core. The XS1-G4, and XS1-G2 specification
can be found in the XS1-G System Specification document. The core archi-
tecture (instruction set) specification can be found in the XS1 Instruction Set
Architecture document.
2 Booting the XS1-L
The standard boot procedure is to first boot Core 0 from either a LLink, JTAG, or
an external ROM or Flash memory that is connected via an SPI interface. The
boot mode is selected by setting pins MODE3 and MODE2:
00 do not boot; used for booting over JTAG
10 boot from ChanEnd 0, enabling LLinks C-H
11 boot from SPI
A further option is to use secure boot for one or more of the cores. Each core
can be configured to boot from a program held in its security module. This is
enabled by setting a bit in the core’s security module and causes the core to
always use secure boot.
2.1 Boot format
When a core is booting over the SPI interface, from a LLink, or from the security
module, the boot ROM built into the L1 reads in a program and stores it in on-
chip RAM starting at the lowest memory location. The program is then started
by transferring control to the lowest location in RAM.
The boot format used for the program to boot from an SPI interface, LLink or
security module is represented as follows:
XS1-L S
S
(0.9)
2008/08/25
YSTEM
PECIFICATION