XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 32

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
6 JTAG
JTAG access to the XS1-L is exactly the same as JTAG to the XS1-G, except
that the MUX has three unconnected entries. It is a two-stage process. A MUX
can be used to:
The state of the MUX is programmed over JTAG. This enables a XS1-L4 to be
constructed by chaining four XS1-L1s, whilst keeping the scan chain short. The
MUX values are:
0000 NC The TMS signal is only connected to the MUX controller. The TDO
0001 SSWITCH The TMS signal is connected to the SSwitch. The TDO output
1xxx CORE0 The TMS signal is connected to XCore0. The TDO output is con-
This encoding is backwards compatible with the XS1-G.
XS1-L S
• Run the scan chain through the core.
• Run the scan chain through the switch.
• Run the scan chain through neither (bypass).
output is taken directly from the MUX controller. In this mode the MUX
controller can be interrogated without knowing the length of the DR in the
devices.
is connected to the SSwitch TDO.
nected to XCore0 TDO.
YSTEM
S
PECIFICATION
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