XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 37

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
XS1-L S
Address
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x18
0x20-0x27
0x30-0x33
0x40-0x43
0x50-0x53
0x60-0x63
0x70-0x73
0x80-0x83
0x90-0x93
0xA0-0xA3
YSTEM
S
PS DBG SSR
PS DBG SPC
PS DBG SSP
PS DBG T NUM
PS DBG T REG
PS DBG TYPE
PS DBG DATA
PS DBG RUN CTRL
PS DBG SCRATCH
PS DBG IBREAK ADDR
PS DBG IBREAK CTRL 0
PS DBG DWATCH ADDR1 DRW
PS DBG DWATCH ADDR2 DRW
PS DBG DWATCH CTRL
PS DBG RWATCH ADDR1 DRW
PS DBG RWATCH ADDR2 DRW
PS DBG RWATCH CTRL
PECIFICATION
(0.9)
DRW
DRW
DRW
DRW
DRW
DRW
DRW
DRW
DRW
DRW
DRW
DRW
DRW
Contents
Saved SR for debug interrupts
Saved PC for debug interrupts
Stores the stack pointer during
debug interrupts
The resource ID of the thread
who’s state is to be read.
Register number to be ac-
cessed by DGETREG.
The type of debug interrupt.
The data causing the debug in-
terrupt.
Determine which threads are
active in when not in debug
mode.
Scratch register for debug inter-
rupts. 0-7
Instruction breakpoint address
0-3
Instruction breakpoint control
register 0-3.
Data watchpoint address 1. 0-3
Data watchpoint address 2. 0-3
Data breakpoint control regis-
ter. 0-3
Resources breakpoint address
1. 0-3
Resources breakpoint address
2. 0-3
Resources breakpoint control
register. 0-3
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