XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 21

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
This results in the following reply message.
A read message is sent as follows:
This results in the following reply message.
The four privileged tokens used to control the switch are defined as follows:
XS1-L S
Name
WRITEC
READC
PSCTRL
SSCTRL
• Three bytes header (two bytes core identifier, one byte channel)
• ACK control token
• END control token
• Two byte header identifying the destination processor/switch
• PSCTRL or SSCTRL token
• READC control token
• Two bytes identifying core that reply should go to
• One byte identifying Channel-end for reply
• Two bytes identifying address within switch (address[15 ... 8], address[7 ... 0])
• END control token
• Three bytes header (two bytes core identifier, one byte channel)
• ACK control token
• Four bytes data read (data[31 ... 24], data[23 ... 16], data[15 ... 8], data[7 ... 0])
• END control token
YSTEM
Value
0xc0
0xc1
0xc2
0xc3
S
PECIFICATION
Description
Write control register
Read control register
PSwitch configuration message
SSwitch configuration message
(0.9)
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