XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 16

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XMOS
15/40
When an XCore wants to send data over a non-routed link it sets the channel-
end destination register to address a tile that differs in place x from the local tile-
id. Destination x is mapped in the lookup table to a direction that is associated
with the required link. The destination channel and processor number have
no relevance and are set to zero. No modifications are needed for this. The
LLink removes the header in non-routed mode. This saves three bytes being
transmitted over the link.
On receiving data on a non-routed link, the link looks up which header to use
in the LLink static forwarding header register (registers 0xA0..0xA7). Each for-
warding header register contains a channel identifier of up to 8 bits (in bits 7 ...
0), a core identifier of up to 8 bits (bits 15 ... 8), and an enable bit (bit 31). On
the XS1-L no processor needs to be specified. The data is transmitted as usual
over the internal link.
3.3.2 Routed links
Before data is transmitted on a stream, the switch sends a header to the desti-
nation tile. The header establishes a route through the interconnect, and sub-
sequent tokens follow the same route until the end-of-message (END) or pause
(PAUSE) token are encountered. The header contains the identifier of the desti-
nation processor, which is encoded using either 16 bits or 3 bits. The processor
address comprises a switch address and a core-number on that switch. The
number of bits used to identify the core on the switch depends on the number of
cores attached to the switch; on a XS1-L there is only one core and no bits are
required, leaving all 16 bits to identify the switch. In the case of four cores on a
switch, the lowest two bits of the address are used to identify the core, and the
highest 14 bits are used to identify the switch.
The header mode can be set in software, by changing the lowest bit of config-
uration register 0x4 (Section 9.3). By default 3-byte mode is used; if the 1-byte
header is used it should be used on all nodes in the system.
Each node has a switch with a configurable identifier and routing table. The
identifier is a bit pattern that (uniquely) identifies this node in the system. When
a stream enters the switch, the destination node identifier is compared bit-by-bit
with the switch-identifier. If all bits match the message is destined for this node
and the message is routed to one of the local tiles using the tile-identifier.
If the switch-identifier is not equal to the stream’s destination-node-identifier, the
XS1-L S
S
(0.9)
2008/08/25
YSTEM
PECIFICATION