PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 99

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

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This data is then fed forward to the destination time slot.
Chapter 5.7 provides examples of such transfers.
3.5.4
Hardware Timer
The EPIC-1 provides a hardware timer which continuously interrupts the
programmable time periods. The timer period can be selected in the range of 250 s up
to 32 ms in multiples of 250 s. Beside the interrupt generation, the timer can also be
used to determine the last look period for 6 and 8-bit signaling channels on IOM-2 and
SLD-interfaces and for the generation of an FSC-multiframe signal (see chapter 5.8.1).
Power and Clock Supply Supervision
The + 5 V power supply line and the clock lines are continuously checked by the EPIC-1
for spikes that may disturb its proper operation. If such an inappropriate clocking or
power failure occurs, the P is requested to reinitialize the device.
3.6
Chapter 2.2.8 provides a detailed functional SACCO-description. This operational
section will therefore concentrate on outlining how to run these HDLC-controllers.
With the SACCO initialized as outlined in chapter 3.8.3, it is ready to transmit and
receive data. Data transfer is mainly controlled by commands from the CPU to the
SACCO via the CMDR-register, and by interrupt indications from SACCO to CPU.
Additional status information, which need not trigger an interrupt, is available in the
STAR-register.
3.6.1
In transmit direction 2
channel. After checking the XFIFO-status by polling the Transmit FIFO Write Enable bit
(XFW in STAR-register) or after a Transmit Pool Ready (XPR) interrupt, up to 32 bytes
may be entered by the CPU to the XFIFO.
The transmission of a frame can then be started issuing a XTF/XPD or XDD command
via the CMDR-register. If prepared data is sent, an end of message indication
Synchronous Transfer
For two channels, all switching paths of figure 47 can also be realized using
Synchronous Transfer. The working principle is that the P specifies an input time slot
(source) and an output time slot (destination). Both source and destination time slots can
be selected independently from each other at either the PCM- or CFI-interfaces. In each
frame, the EPIC-1 first transfers the serial data from the source time slot to an internal
data register from where it can be read and if required overwritten or modified by the P.
Semiconductor Group
Special Functions
SACCO-A/B
Data Transmission in Interrupt Mode
32-byte FIFO-buffers (transmit pools) are provided for each
99
Operational Description
PEB 20550
PEF 20550
P after
01.96