PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 305

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

In this case the monitor channel protocol is a non handshake procedure which can be
used to exchange one byte of information at a time between the ELIC and a layer-1
device such as the IBC (PEB 2095) or the IEC-T (PEB 2090).
Data bytes to be transmitted are sent once in the downstream monitor channel. Since
the monitor channel is idle (FF) when no data is being transmitted, the receiving device
accepts only valid data bytes which are different from FF. If a message shall be sent
back to the ELIC, this must occur in the frame following the frame of reception.
SLD Interface Protocol
The transfer of control information over the feature control channel of an SLD interface
e.g. for programming the coefficients to a SICOFI (PEB 2060) device is also performed
without a handshake procedure. Data is transmitted and received synchronous to the
8 kHz frame at a speed of one data byte per frame.
The MF handler of the ELIC supports all three kinds of protocols. A bidirectional 16 byte
FIFO, the MFFIFO, serves as data buffer for outgoing and incoming MF messages in all
protocol modes. This implies that the MF communication is always performed on a half-
duplex basis.
Differentiation between IOM-2 and IOM-1/SLD modes is made via the MF Protocol
Selection bit MFPS in the Operation Mode Register OMDR.
IOM
Since the IOM-1 and SLD protocols are very similar, they are treated by the ELIC in
exactly the same way i.e. without handshake protocol. The only processing difference
concerns the involved upstream timeslot when receiving data:
When configured as IOM interface (CFI modes 0, 1 or 2), the CFI ports consist of
separate upstream (DU) and downstream (DD) lines. In this case MF data is transmitted
on DD and received on DU of the same CFI timeslot.
When configured as SLD interface (CFI mode 3), the CFI ports consist of bidirectional
lines (SIP). The first four timeslots of the frame are used as downstream timeslots and
the last four as upstream timeslots. In this case the MF data is transmitted in the
downstream feature control timeslot and received on the same CFI line but four
timeslots later in the upstream feature control timeslot.
CFI timeslots which should be processed by the MF handler must first be initialized as
MF/CS channels with appropriate codes in the Control Memory Code Field (refer to
chapter 5.5.1).
Except for broadcast operation, communication over the MF channel is only possible
with one subscriber circuit at a time. The MF handler must therefore be pointed to that
particular timeslot via the address register MFSAR.
Normally MF channel transfers are initiated by the ELIC (master). The subscriber circuits
(slaves) will only send back monitor messages upon a request from the master device.
Semiconductor Group
®
-1 Interface Protocol
305
Application Hints
PEB 20550
PEF 20550
01.96