PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 217
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PEF20550HV21XT
Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet
1.PEF20550HV21XT.pdf
(407 pages)
Specifications of PEF20550HV21XT
Lead Free Status / Rohs Status
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Figure 68 shows the relationship between the DCL input and the generated RCL for the
different prescaler divisors in case CMD1:CSS = 1:
Figure 68
Clock Signal Timing for the Different Prescaler Divisors if CMD1:CSS = 1
CFI Clock Output Rate CMD2:COC
This feature applies only if the configurable interface is clocked and synchronized via the
PCM interface clock and framing signals (PDC, PFS), i.e. if CMD1:CSS = 0.
In this case the ELIC delivers an output clock signal at pin DCL with a frequency identical
to or double the selected CFI data rate:
For CMD2:COC = 0, the frequency of DCL is identical to the CFI data rate
For CMD2:COC = 1, the frequency of DCL is twice the CFI data rate
Semiconductor Group
FSC
FSC
DCL
RCL
RCL
RCL
RCL
RCL
RCL
(all CFI modes)
(CFI modes 0 and 3 only!)
217
Conditions:
CMD1 : CSM = 1
CMD1
CFI Modes 0, 1 and 3
CFI Mode 2
CFI Modes 0, 1 and 3
CFI Mode 2
CFI Modes 0, 1 and 3
CFI Mode 2
:
CSM
Application Hints
=
0
PEB 20550
PEF 20550
ITT08047
01.96
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