PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 363

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Write
Write
6.1.4.2 Confirmation of Line Activation
Write
Write
6.1.4.3 Enabling the Arbiter
Write
The D-channel arbiter is now resetting the downstream arbitration control bit of IOM-2
port 0, channel 0 to ‘available’ (C/I code ‘1000’)
D-channel data from subscriber A.
6.1.4.4 Build-up of Layer 2
With layer-1 communications established, terminal A initiates layer-2 build-up with an
UI-frame; on receiving this UI-frame, the ELIC will signal an interrupt:
Read
Read
Read
Read
Assigning an ID to the terminal:
Write
Write
Write
Read
Next, the terminal indicates that it wishes to use extended asynchronous-balanced
mode. This message, as well as further D-channel communication between terminal and
ELIC, is shown in abbreviated form:
Received at RFIFO of SACCO-A from terminal A:
Sent from XFIFO of SACCO-A to terminal A:
Semiconductor Group
MADR = F3
MAAR = 08
MACR = 48
DCE0 = 01
ISTA
ISTA_A= 80
RBCL = 09
RFIFO = UI-frame: ID Request
CMDR = 80
XDC
XFIFO =
CMDR = 0A
ISTA_A= 10
= 02
= 00
RSTA byte= 80
H
H
H
H
H
H
H
H
H
H
H
set downstream C/I code to ‘1100’ (active, but with the
arbitration control bit set to ‘blocked’)
downstream CM address: port 0, TS2
write to the CM data field
enable the D-channel arbiter to monitor the D-channel of
IOM-2 port 0, channel 0
interrupt at SACCO-A
Receive Message End (RME) interrupt
9 byte in RFIFO: 8 bytes received + RSTA byte
reset CPU accessible portion of RFIFO
direct SACCO-A transmission to IOM-2 port 0, channel 0
UI-frame: ID Assignment (8 bytes)
transmit transparent frame; transmit message end
Transmit Pool Ready (XPR)
H
frame received from IOM-2 port 0, channel 0 OK
363
the ELIC is now ready to receive
U-frame: SABME
Unnumbered Acknowledge
Application Notes
PEB 20550
PEF 20550
01.96