PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 253
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PEF20550HV21XT
Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet
1.PEF20550HV21XT.pdf
(407 pages)
Specifications of PEF20550HV21XT
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W:MACR
wait for STAR:MAC = 0
R:MADR
W:MACR
wait for STAR:MAC = 0
R:MADR
W:MAAR
W:MACR
5.3.3.4 Access to the Control Memory Code Field
The 4 bit code field of the control memory (CM) defines the functionality of a CFI timeslot
and thus the meaning of the corresponding data field.
There are codes for switching applications, preprocessed applications and for direct P
access applications (see table 40).
This 4 bit code, written to the MACR:CMC3 … 0 bit positions, will be transferred to the
CM code field by selecting MACR:MOC = 111X. The 8 bit MADR value is at the same
time transferred to the CM data field.
The Procedure for Writing to the CM Code and Data Fields with a Single
Command is
W:MADR = value for data field
W:MAAR = CFI timeslot address encoded according to figure 84
W:MACR =
CMC3 … 0 CM code, refer to table 40
Examples
In CFI mode 2, CFI timeslot 123 has been initialized as a switched channel. The CM data
field value therefore represents a pointer to the PCM interface.
In a first step, the involved upstream and downstream PCM timeslots shall be
determined:
W:MAAR
W:MAAR
In the next step a new timeslot assignment (to PCM port 1, timeslot 34, PCM mode 1)
shall be made for the upstream connection:
W:MADR
Semiconductor Group
= 1111 1011
= 1100 1000
= value
= 0111 1011
= 1100 1000
= value
= 1100 0110
= 1111 1011
= 0100 1000
bit 7
0
1
B
B
B
B
B
B
B
; address of upstream CFI timeslot 123
; read back command
; encoded according figure 84
; address of downstream CFI timeslot 123
; read back command
; encoded according figure 84
; upstream PCM timeslot 34, port 1
; address of upstream CFI timeslot 123
; write command
1
253
1
CMC3
CMC2
Application Hints
CMC1
PEB 20550
PEF 20550
bit 0
CMC0
01.96
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