PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 124

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

IWD
IDA
IEP
EXB
ICB
EXA
ICA
IWD and IDA are reset when reading ISTA. The other bits are reset when reading the
corresponding local ISTA- or EXIR-register.
4.2
4.2.1
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
IWD
Interrupt Top Level
Interrupt Status Register (ISTA)
Interrupt Watchdog Timer.
The watchdog timer is expired and an external reset (RESIN) was generated.
The software failed to program the bits WTC1 and WTC2 in the correct
sequence.
Interrupt D-channel Arbiter.
The suspend counter expired while the arbiter was in the state "expect frame".
The affected D-channel can be determined by reading register ASTATE.
Interrupt EPIC-1,
detailed information is indicated in register ISTA_E.
Extended interrupt SACCO-B,
detailed information is indicated in register EXIR_B.
Interrupt SACCO-B,
detailed information is indicated in register ISTA_B.
Extended interrupt SACCO-A,
detailed information is indicated in register EXIR_A.
Interrupt SACCO-A,
detailed information is indicated in register ISTA_A.
IDA
H
IEP
EXB
124
ICB
read
read
Detailed Register Description
EXA
address: 41
address: 82
ICA
PEB 20550
PEF 20550
bit 0
H
H
0
01.96