PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 141

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TSN6..0
4.6.9
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: FF
CBN7..0
4.6.10 Configurable Interface Time Slot Adjustment Register (CTAR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: If CMD1:CSS = 0, the CFI-frame will be shifted - together with the FSC-output
Semiconductor Group
bit 7
bit 7
CBN7
0
signal - with respect to PFS. The position of the CFI-frame relative to the
FSC-output signal is not affected by these settings, but is instead determined by
CMD2:FC2..0. If CMD1:CSS = 1, the CFI-frame will be shifted with respect to the
FSC-input signal.
Configurable Interface Bit Number Register (CBNR)
CFI-Bit Number 7..0.
The number of bits that constitute a CFI-frame must be programmed to
CMD2, CBNR:CBN9..0 as indicated below.
CBN9..0 = number of bits
For a 8-kHz frame structure, the number of bits per frame can be derived
from the data rate by division with 8000.
Time Slot Number.
The CFI-framing signal (PFS if CMD1:CSS = 0 or FSC if CMD1:CSS = 1)
marks the CFI time slot called TSN according to the following formula:
TSN6..0 = TSN + 2
E.g.: If the framing signal is to mark time slot 0 (bit 7), CTAR must be set to
02
CBN6
TSN6
H
H
(CBSR to 20
H
CBN5
TSN5
H
).
CBN4
TSN4
1
141
CBN3
TSN3
read/write
read/write
read/write
read/write
Detailed Register Description
CBN2
TSN2
address: 18
address: 19
address: 30
address: 32
CBN1
TSN1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
CBN0
TSN0
01.96