PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 144

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.6.13 Memory Access Control Register (MACR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
With the MACR the P selects the type of memory (CM or DM), the type of field (data or
code) and the access mode (read or write) of the register access. When writing to the
control memory code field, MACR also contain the 4 bit code (CMC3..0) defining the
function of the addressed CFI time slot.
RWS
MOC3..0 Memory Operation Code.
CMC3..0
Note: Prior to a new access to any memory location (i.e. writing to MACR) the
1. Writing data to the upstream DM-data field (e.g. PCM-idle code).
MACR:
MOC3..0 defines the bandwidth and the position of the subchannel as shown below:
Semiconductor Group
bit 7
RWS
RWS
Reading data from the upstream or downstream DM-data field.
STAR:MAC bit must be polled for ’0’.
Read/Write Select.
0…write operation on control or data memories
1…read operation on control or data memories
Control Memory Code.
These bits determine the type and destination of the memory operation as
shown below.
MOC3..0
0000
0001
0011
0010
0111
0110
0101
0100
MOC3
MOC3
H
MOC2
MOC2
MOC1
MOC1
Transferred Bits
–
bits 7..0
bits 7..4
bits 3..0
bits 7..6
bits 5..4
bits 3..2
bits 1..0
144
MOC0
MOC0
CMC3
read/write
read/write
Detailed Register Description
CMC2
0
Channel Bandwidth
–
64 kBit/s
32 kBit/s
32 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
address: 00
address: 00
CMC1
0
PEB 20550
PEF 20550
bit 0
H
H
CMC0
0
01.96