PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 247
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PEF20550HV21XT
Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet
1.PEF20550HV21XT.pdf
(407 pages)
Specifications of PEF20550HV21XT
Lead Free Status / Rohs Status
Supplier Unconfirmed
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W:MADR
W:MAAR
W:MACR
The idle code can, of course, only be transmitted on the TxD# line if the corresponding
tristate bits are enabled (refer to chapter 5.3.3.2):
W:MADR
W:MAAR
W:MACR
For test purposes the idle code can also be read back:
W:MAAR
W:MACR
wait for STAR:MAC = 0
R:MADR
In PCM mode 2 the idle pattern ‘0110’ shall be transmitted in bit positions 3 … 0 of
timeslot 63, bits 7 … 4 shall be tristated:
W:MADR
W:MAAR
W:MACR
Programming of the desired tristate functions:
W:MADR
W:MAAR
W:MACR
Examples
In PCM mode 0 the idle code ‘1010 0101
Semiconductor Group
= 1010 0101
= 1100 0000
= 0000 1000
= XXXX 1111
= 1100 0000
= 0110 0000
= 1100 0000
= 10XX X000
= 1010 0101
= XXXX 0110
= 1011 1111
= 0001 0000
= XXXX 0011
= 1011 1111
= 0110 0000
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
; idle code
; address of upstream PCM timeslot 16 of port 0
: write access, MOC code '0001'
; all 8 bits of addressed timeslot to low impedance
; address of upstream PCM timeslot 16 of port 0
: write access, MOC code ‘1100’
; address of upstream PCM timeslot 16 of port 0
: read access, MOC code '0XXX'
; idle code
; idle code
; address of upstream PCM timeslot 63
; write access, MOC code ‘0010’
; bits 7 … 4 to high impedance, bits 3 … 0 to low
; address of upstream PCM timeslot 63
; write access, MOC code ‘1100’
according to figure 84
according to figure 84
according to figure 84
according to figure 84
impedance
according to figure 84
B
247
’ shall be transmitted in timeslot 16 of port 0:
Application Hints
PEB 20550
PEF 20550
01.96
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