PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 197

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

transmitted directly to the CFI timeslot i.e. to the control memory. This value will then be
transmitted repeatedly in each frame until a new value is loaded.
If the 4 bit C/I channel option is selected, the two D channel bits can either be tristated
by the ELIC (decentral D channel handling scheme) or they can be switched
transparently from any 2 bit sub-timeslot position at the PCM interface (central D channel
handling scheme).
In upstream direction, the P can read the received 4, 6, or 8 bit C/I or Signaling value
directly from the CFI timeslot i.e. from the control memory. In addition the Control/
Signaling handler checks all received C/I and Signaling channels for changes. Upon a
change:
– an interrupt is generated,
– the address of the involved CFI timeslot is stored in a 9 byte FIFO (CIFIFO) and
– the new value is stored in the control memory.
The CIFIFO serves to buffer the address information in order to increase the P latency
time.
The change detection mechanism is based on a single last look procedure for 4 bit C/I
channels and on a double last look procedure for 6 and 8 bit C/I or Signaling channels.
The single last look period is fixed to 125 s, whereas the double last look period is
programmable from 125 s to 32 ms. The last look period is programmed using the ELIC
timer.
With the single last look procedure, each C/I value change immediately leads to a valid
change and thus to an interrupt.
With the double last look procedure, a C/I or Signaling value change must be detected
two times at the sampling points of the last look interval before a valid change is
recognized and an interrupt is generated.
If the 4 bit C/I channel option is selected, the two D channel bits can either be ignored
by the ELIC (decentral D channel handling scheme) or they can be switched
transparently to any 2 bit sub-timeslot position at the PCM interface (central D channel
handling scheme).
In downstream direction, the P can write the 4, 6 or 8 bit C/I or Signaling value to be
Semiconductor Group
197
Application Hints
PEB 20550
PEF 20550
01.96