PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 170

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

MDS1..0
ADM
4.7.7
Access in demultiplexed
Access in multiplexed
Reset value: 00
Note: In extended transparent mode 0 and 1 the bit MODE:RAC must be reset to enable
CFT
Semiconductor Group
bit 7
P-interface mode:
P-interface mode:
MDS1
fully transparent reception.
Mode Register (MODE)
Mode Select.
The operating mode of the HDLC-controller is selected.
00…auto-mode
01…non-auto-mode
10…transparent mode (D-channel arbiter)
11…extended transparent mode
Address Mode.
The meaning of this bit varies depending on the selected operating mode:
Continuous Frame Transmission.
1…When CFT is set the XPR-interrupt is generated immediately after the
0…Otherwise the XPR-interrupt is delayed until the transmission is
Auto-mode / non-auto mode
Defines the length of the HDLC-address field.
0…8-bit address field,
1…16-bit address field.
Transparent mode
0…no address recognition: transparent mode 0 (D-channel arbiter)
1…high byte address recognition: transparent mode 1
Extended transparent mode
0…receive data in RAL1: extended transparent mode 0
1…receive data in RFIFO and RAL1: extended transparent mode 1
MDS0
CPU accessible part of XFIFO is copied into the transmitter section.
completed (D-channel arbiter).
H
ADM
CFT
read/write
read/write
170
RAC
address: (Ch-A/Ch-B): 22
address: (Ch-A/Ch-B): 44
Detailed Register Description
0
0
PEB 20550
PEF 20550
H
H
bit 0
/62
/C4
TLP
H
H
01.96