PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 200

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

0
0
1
1
the channel capacity of the ELIC is constant (128 channels per direction), the PCM mode
also influences the maximum possible data rate. In each PCM mode a minimum data
rate as well as a minimum data rate stepping are specified.
It should also be noticed that there are some restrictions concerning the PCM to CFI data
rate ratio which may affect some applications. These restrictions are described in
chapter 5.2.2.3.
The table below summarizes the specific characteristics of each PCM mode (DR = PCM
data rate):
Table 24
Operation Modes at the PCM Interface
PMD1
Note: The label is used to specify a PCM port (logical port) when programming a
PCM Clock Rate PMOD:PCR
The PCM interface is clocked via the PDC pin. If PCR is set to logical 0, the PDC
frequency must be identical to the selected data rate (single clock operation). If PCR is
set to logical 1, the PDC frequency must be twice the selected data rate (double clock
operation). Note that in PCM mode 2, only single clock rate operation is allowed.
In PCM mode 0 for example, PCR can be set to 1 to operate at up to four 2048 kBit/s
PCM highways with a PCM clock of 4096 kHz.
PCM Bit Number PBNR:BNF7 … BNF0
The PCM data rate is determined by the clock frequency applied to the PDC pin and the
clock rate selected by PMOD:PCR. The number of bits which constitute a PCM frame
can be derived from this data rate by dividing by 8000 (8 kHz frame structure).
If the PCM interface is for example operated at 2048 kBit/s, the frame would consist of
256 bits or 32 timeslots.
Semiconductor Group
switching function. It should not be confused with the physical port number which
refers to actual hardware pins. The relationship between logical and physical port
numbers is given in table 30 and is illustrated in figure 64.
PMD0 PCM
0
1
0
1
Mode
0
1
2
3
Number (Label)
of Logical Ports
4 (0 … 3)
2 (0 … 1)
1
2 (0 … 1)
200
256
512
1024
512
min. max.
Data Rate
[kBit/s]
2048
4096
8192
4096 512
Data Rate
Stepping
[kBit/s]
256
512
1024
Application Hints
PDC
Frequency
(Clock Rate)
DR, 2
DR, 2
DR
DR, 2
PEB 20550
PEF 20550
DR
DR
DR
01.96