PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 302

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
The above programming sequence can for example be performed during the
initialization phase of the ELIC. Once the CFI timeslots have been loaded with the
appropriate codes ('1010' in timeslot 6 and ‘1011’ in timeslot 7), an access to the
downstream SIG channel (timeslot 7) can be accomplished simply by writing a new
value to the address of timeslot 6:
W:MADR
W:MAAR
W:MACR
5.5.2.3 Access to the Upstream C/I and SIG Channels
If two consecutive upstream CFI timeslots, starting with an even timeslot number, are
programmed as MF and CS channels, the P can read the received 4, 6 or 8 bit C/I or
SIG values simply by reading the upstream CM data field.
Two cases can be distinguished:
When a 4 bit Command/Indication handling scheme is selected, the C/I value received
in the odd CFI timeslot can be read from the even CM address. This value is sampled in
each frame (every 125 s). Each change is furthermore indicated by an ISTA_E:SFI
interrupt and the address of the corresponding even CM location is stored in the CIFIFO.
Since the MSB of the CIFIFO is set to 1 for a valid entry (SBV = 1), the value read from
the CIFIFO can directly be copied to MAAR in order to read the upstream CM data field
which also requires an MSB set to 1 (U/D = 1).
When a 6 or 8 bit signaling scheme is selected, the received SIG value is sampled at
intervals of 125 s or (TVAL + 1)
CM address. The P can access the actual value simply by reading this even CM data
field location. Additionally, a ‘stable value’, based on the double last look algorithm is
generated: in order to assure that erroneous bit changes at the sampling time point do
The value written to MADR should have the following format:
4 bit C/I value: MADR = 1 1 _ _ _ _ 1 1
6 bit SIG value: MADR = _ _ _ _ _ _ 1 1
8 bit SIG value: MADR = _ _ _ _ _ _ _ _
Examples
In CFI mode 0 the downstream timeslots 6 and 7 of port 2 shall be initialized as MF and
CS channels, 6 bit signaling scheme. The initialization value shall be ‘010101’:
W:MADR
Semiconductor Group
= 0101 0111
= 0001 1100
= 0111 1010
= XXXX XXXX
= 0001 1101
= 0111 1011
= 1100 1111
= 0001 1100
= 0100 1000
B
B
B
B
B
B
B
B
B
; SIG value ‘010101’
; downstream, port 2, timeslot 6
; write CM code + data fields, CM code ‘1010’
; don’t care
; downstream, port 2, timeslot 7
; write CM code + data fields, CM code ‘1011’
; new SIG value ‘110011’
; downstream, port 2, timeslot 6
; write CM DF, MOC = 1001
250 s and stored as the “actual value” at the even
B
B
B
302
Application Hints
PEB 20550
PEF 20550
01.96