PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 89

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The selection is performed via pin ALE as follows:
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects interface type (3). A return to one of the other interface
types is only possible by issuing a hardware reset.
With an active CSS, the addressing selects the FIFOs and registers of the SACCO-A or
SACCO-B. With an active CSE, the addressing selects the memories and/or registers of
3
The ELIC, designed as a flexible line-card controller, has the following main applications:
– Digital line cards, with the CFI typically configured as IOM-2, IOM-1 (MUX) or SLD.
– Analog line cards, with the CFI typically configured as IOM-2 or SLD.
– Key systems, where the ELIC’s ability to mix CFI-configurations is utilized.
To operate the ELIC the user must be familiar with the device’s microprocessor
interface, interrupt structure and reset logic. Also, the operation of the ELIC’s component
parts should be understood.
The devices major components are the EPIC-1, the SACCO-A and SACCO-B, and the
D-channel arbiter. While EPIC-1, SACCO-A and SACCO-B may all be operated
independently of each other, the D-channel arbiter can be used to interface the
SACCO-A to the CFI of the EPIC-1. This mode of operation may be considered to utilize
the ELIC most extensively. The initialization example, with which this operational
description closes, will therefore set the ELIC to operate in this manner.
3.1
The ELIC is programmed via an 8-bit parallel interface that can be selected to be
the
– top level interrupt,
– EPIC-1,
– D-channel arbiter,
– parallel ports, or
– watchdog timer.
Semiconductor Group
(1) Motorola type, with control signals DS, R or W, and CSS or CSE.
(2) Siemens / Intel non-multiplexed bus type, with control signals WR, RD,
(3) Siemens / Intel multiplexed address/data bus type, with control signals
ALE tied to
ALE tied to
Edge on ALE
and CSS or CSE.
ALE, WR, RD, and CSS or CSE.
Operational Description
Microprocessor Interface Operation
V
V
DD
SS
(3)
(2)
(1)
89
Operational Description
PEB 20550
PEF 20550
01.96