PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 82

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.2.8.1 Upstream Direction
In upstream direction the arbiter assigns the receive channel of SACCO-A to one
subscriber terminal.
It uses an unidirectional control channel to indicate the terminals whether their
D-channels are available or blocked. The control channel is implemented using different
existing channel structures to close the transmission path between the line card HDLC-
controller and the HDLC-controller in the subscriber terminal. On the line card, the
control channel is either integrated in the C/I-channel or transmitted in the MR-bit
depending on a programming of bit AMO:CCHH (OCTAT-P -> C/I channel, IBC ->
MR-bit), see also chapter 1.6.1.2.
Arbiter State Machine
The D-channel assignment is performed by the arbiter state machine (ASM),
implementing the following functionality.
(0) After reset or when SACCO-A clock mode is not 3 the ASM is in the state
(1) When the receiver of SACCO-A is reset and clock mode 3 is selected the ASM
(2) Upon the detection of the first ’0’ the ASM enters the state "expect frame". When
(3) When the counter underflows before the state "expect frame" was left, the
(4) When seven consecutive '1's are detected in the state "expect frame" before the
Semiconductor Group
"suspended". The user can initialize the arbiter and select the appropriate SACCO
clock mode (mode 3).
enters the state "full selection". In this state all D-channels enabled in the
D-channel enable registers (DCE) are monitored.
simultaneously ’0’s are detected on different IOM-2 channels, the lowest channels
number is selected. Channel and port address of the related subscriber are latched
in arbiter state register (ASTATE), the receive strobe for SACCO-A is generated
and the DCE-values are latched into a set of slave registers (DCES). Additionally a
suspend counter is loaded with the value stored in register SCV. The counter is
decremented after every received byte (4 IOM-frames).
corresponding D-channel is considered to produce permanent bit errors (typical
pattern: …111011101011…). The ASM emits an interrupt, disables the receive
strobe and enters the state "suspended" again. The user can determine the
affected channel by reading register ASTATE. In order to reactivate the ASM the
user has to reset the SACCO-A receiver.
suspend counter underflows the ASM changes to the state "limited selection".
The previously detected '0' is considered a single bit error (typical pattern:
…11111101111111111…). The receive strobe is turned off and the DCES-bit
related to the corresponding D-channel is reset, i.e. the subscriber is temporarily
excluded of the priority list.
82
Functional Description
PEB 20550
PEF 20550
01.96