PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 171

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PU
SC1..0
ODS
RAC
TLP
4.7.8
Access in demultiplexed
Access in multiplexed
Reset value: 00
Semiconductor Group
bit 7
P-interface mode:
P-interface mode:
PU
Channel Configuration Register 1 (CCR1)
Receiver Active.
Via RAC the HDLC-receiver can be activated/deactivated.
0…HDLC-receiver inactive
1…HDLC-receiver active
In extended transparent mode 0 and 1 RAC must be reset (HDLC-receiver
disabled) to enable fully transparent reception.
Test Loop.
When set input and output of the HDLC-channel are internally connected.
(transmitter channel A - receiver channel A
transmitter channel B - receiver channel B)
TXDA/B are active, RXDA/B are disabled.
Power-Down Mode.
0…power-down (standby), the internal clock is switched off.
1…power-up (active).
Serial Port Configuration
00…point to point configuration,
01…bus configuration, timing mode 1, data is output with the rising edge of
11…bus configuration, timing mode 2, data is output with the falling edge
Output Driver Select.
Defines the function of the transmit data pin (TxDA/B).
0…TxDA/B-pin open drain output
1…TxDA/B-pin push-pull output
SC1
Nevertheless, register read/write access is possible.
H
the data clock on pin TxDA/B and evaluated 1/2 clock period later with
the falling clock edge at pin CxDA/B
of the data clock and evaluated with the next falling clock edge.
Thus one complete clock period is available between data output and
evaluation.
SC0
ODS
read/write
read/write
171
ITF
address: (Ch-A/Ch-B): 2F
address: (Ch-A/Ch-B): 5E
Detailed Register Description
CM2
CM1
PEB 20550
PEF 20550
H
H
bit 0
/6F
/DE
CM0
H
H
01.96