PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 100

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(CMDR:XME) must also be set. If transparent or direct data is sent, CMDR:XME may but
need not be set. If CMDR:XME is not set, the SACCO will repeatedly request for the next
data block by means of a XPR-interrupt as soon as the CPU accessible part of the
XFIFO is available. This process will be repeated until the CPU indicates the end of
message per command, after which frame transmission is ended by appending the CRC
and closing flag sequence.
If no more data is available in the XFIFO prior to the arrival of XME, the transmission of
the frame is terminated with an abort sequence and the CPU is notified per interrupt
(EXIR:XDU). The frame may also be aborted per software (CMDR:XRES).
Figure 49 outlines the data transmission sequence from the CPU’s point of view:
Figure 49
Interrupt Driven Transmission Sequence (flow diagram)
Semiconductor Group
Command
XTF or XDD
N
N
(up to 32 Bytes)
Write Data
to XFIFO
XTF/XPD or XDD
Command XME+
Pool Ready
Massage
Transmit
START
End of
END
?
?
Y
Y
100
ITD05847
XPR Interrupt or Set
XFW Bit in STAR Register
Operational Description
PEB 20550
PEF 20550
01.96