PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 293

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PEF20550HV21XT

Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF20550HV21XT

Lead Free Status / Rohs Status
Supplier Unconfirmed
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
Example
In CFI mode 0, timeslots 2 and 3 of port 0 shall be initialized for 6 bit signaling channel
handling:
W:MADR
Semiconductor Group
= 0100 0111
= 0000 1000
= 0111 1010
= XXXX XXXX
= 0000 1001
= 0111 1011
= 1101 1111
= 1000 1000
= 0111 1010
= 1101 1111
= 1000 1001
= 0111 1010
B
B
B
B
B
B
B
B
B
B
B
B
; SIG value ‘010001’
; downstream even TS, port 0 timeslot 2
; write CM code + data fields, CM code ‘1010’
; don’t care
; downstream odd TS, port 0 timeslot 3
; write CM code + data fields, CM code ‘1011’
; expected SIG value ‘110111’
; upstream even TS, port 0 timeslot 2
; write CM code + data fields, CM code ‘1010’
; expected SIG value ‘110111’
; upstream odd TS, port 0 timeslot 3
; write CM code + data fields, CM code ‘1010’
293
Application Hints
PEB 20550
PEF 20550
01.96

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