PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 189

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DCEn7..0 D-Channel Enable bits channel 7-0, IOM-port n.
4.8.8
Access in demultiplexed P-interface mode:
BCT
PAD1..0
CHAD2..0 Channel Address, defines the transmit IOM-channel when BCT = 0.
4.8.7
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
bit 7
DCE37
0
D-Channel Enable Register IOM-Port 3 (DCE3)
Transmit D-Channel Address Register (XDC)
0…D-channel i on IOM-port n is disabled for data reception. The control
1…D-channel i on IOM-port n is enabled for data reception.
Broadcast Transmission, BCT = 1 enables broadcast transmission. The
transmitted frame is send to all channels enabled in the registers BCG0-3.
Port address, defines the transmit IOM-port when BCT = 0.
DCE36
channel of a disabled D-channel is not manipulated by the control
channel master. It passes the value stored in the EPIC-1 control memory
(C/I or MR must = "blocked"). The disabling of a D-channel has an
immediate effect also when the channel is active. In this case the
transmitter (HDLC-controller in the subscriber terminal) is forced to abort
the current frame.
The control channel of an enabled D-channel is manipulated
a) by the control channel master, if AMO:CCHM = 1,
b) directly via DCE, if AMO:CCHM = 0.
H
H
0
DCE35
BCT
DCE34
PAD1
189
DCE33
PAD0
read/write
read/write
read/write
read/write
Detailed Register Description
CHAD2
DCE32
address: 66
address: 67
address: CC
address: CE
CHAD1
DCE31
PEB 20550
PEF 20550
bit 0
bit 0
H
H
CHAD0
H
H
DCE30
01.96