PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 103

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.6.4
If the RFIFO contains 32 bytes, the SACCO autonomously requests a block DMA-
transfer by activating the DRQR-line. This forces the DMA-controller to continuously
perform bus cycles until 32 bytes are transferred from the SACCO to the system
memory.
If the RFIFO contains less than 32 bytes (one short frame or the last part of a long frame)
the SACCO requests a block data transfer depending on the contents of the RFIFO
according to the following table:
RFIFO Contents (in bytes)
1, 2, 3
4, 5, 6, 7
8 - 15
16 - 32
After the DMA-controller has been set up for the reception of the next frame, the CPU
must issue a RMC-command to acknowledge the completion of the receive frame
processing. Prior to the reception of this RMC, the SACCO will not initiate further DMA-
cycles by activating the DRQR-line.
The following figure gives an example of a DMA controlled reception sequence
supposing that a long frame (66 bytes) followed by a short frame (6 byte) are received.
Figure 53
DMA-Driven Reception Example
Semiconductor Group
Serial
Interface
SACCO
CPU
Interface
Data Reception in DMA-Mode
Receive 66 Bytes
32
DRQR (32)
RD
32
68 DMA Read Cycles
DRQR (32)
2
RD
Receive
6 Bytes
6
DRQR (4)
RD
103
DMA Request (in bytes)
4
8
16
32
RME
Count
Byte
(67)
RMC
DRQR (8)
RD
Operational Description
RME
Count
Byte
(7)
PEB 20550
PEF 20550
RMC
ITD05850
01.96