PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 323

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

synchronously to the frame repetition rate. The synchronous transfer is controlled by the
synchronous transfer registers.
The information is buffered in the synchronous transfer data register STDA (STDB). It is
copied to STDA (STDB) from a data or control memory location pointed to by the content
of the synchronous receive register SARA (SARB) and copied from the STDA (STDB)
to a data or control memory location pointed to by the content of the synchronous
transfer transmit register SAXA (SAXB).
The SAXA (SAXB) and SARA (SARB) registers identify the interface (PCM or CFI) as
well as the timeslot and port numbers of the involved channels according to figure 84.
Control bits in the synchronous transfer control register STCR allow restricting the
synchronous transfer to one of the possible sub-timeslots and enables or disables the
synchronous transfer utility.
For example, it is possible to read information via the downstream data memory from the
PCM interface input to the STDA (STDB) register and to transmit it from this register
back via the upstream data memory to the PCM interface output, thus establishing a
PCM - PCM loop. Similarly the synchronous transfer facility may be used to loop back
configurable interface channels or to establish connections between the CFI and PCM
interfaces. While the information is stored in the data register STDA (STDB), it may be
read and or modified by the P.
5.7
The synchronous transfer utility allows the synchronous exchange of information
between the PCM interface, the configurable interface, and the P interface for two
independent channels (A and B). The P can thus monitor, insert, or manipulate the data
Semiconductor Group
Synchronous Transfer Utility
323
Application Hints
PEB 20550
PEF 20550
01.96