PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 86

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

When a D-channel is enabled in the DCE-register and available, the control channel
master takes priority over the C/I- (MR) values stored in the EPIC-1 control memory and
writes out either MR = 1 or C/I = x0xx. When a D-channel is enabled but blocked, the
control channel master simply passes the C/I- (MR) values which are stored in the
EPIC-1 control memory. These values should have been programmed as MR = 0 or C/
I = x1xxx.
When a D-channel is disabled in the DCE-register the control channel master simply
passes the C/I- (MR) values which are stored in the EPIC-1 control memory. This gives
the user the possibility to exclude a D-channel from the arbitration but still decide
whether the excluded channel is available or blocked.
Overview of different conditions for control channel handling/information sent to
subscribers:
Clock Mode
ASM State
CCHM
Subscriber in
DCEs
Information
sent to
Subscribers =
"available" or
"blocked"
2.2.8.2 Downstream Direction
In downstream direction no channel arbitration is necessary because the sequentiality
of the transmitted frames is guaranteed.
In order to define IOM-channel and port number to be used for a transmission, the
transmit channel selector (TCHS) provides a transmit address register (XDC) which the
user has to write before a transmit command (XTF) is executed. Depending on the
programming of the XDC-register the frame is transmitted in the specified D-channel or
send as broadcast message to the broadcast group defined in the registers BCG1-4.
Due to the continuous frame transmission feature of the SACCO, the full 16-kbit/s
bandwidth of the D-channel can be utilized, even when addressing different subscribers.
Note: The broadcast group must not be changed during the transmission of a frame
Semiconductor Group
3
Not suspended
’1’ = enabled
Enabled
According
D-channel
Arbiter
State
(CCM)
to the
Disabled
Content of
the
EPIC-1
Control
Memory-
(C/I or
MR)
Suspended
’1’ = enabled
X
Enabled
Content of
the
EPIC-1
Control
Memory-
(C/I or
MR)
86
Content of
the
EPIC-1
Control
Memory-
(C/I or
MR)
Disabled
Functional Description
X
X
’0’ = disabled
Enabled
Available!
PEB 20550
PEF 20550
Disabled
Content
of the
EPIC-1
Control
Memory-
(C/I or
MR)
01.96