MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 95

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
Table 34.
September 2007
Order Number: 318146-001
After NMI assertion the IPMC logs SEL event from event-only sensor "Forced NMI".
Only one offset is logged: offset 01 = "State Asserted". Event data 2 contains NMI
cause, as defined in
NMI causes
Value
01h
02h
03h
04h
• Receiving a Set NMI Source command issued from one of the command interfaces.
• IERR action - when IERR action is configured to assert NMI the IPMC will generate
the NMI signal on detection of IERR error from CPU.
NMI cause
IPMI watchdog pre-timeout action
PEF action
Chassis command “Pulse Diagnostic Interrupt”
IERR action. Used and logged when NMI has been generated in response to IERR.
Note: this requires configure IERR action as “NMI”
Table
34.
Intel NetStructure
®
MPCBL0050 Single Board Computer
Technical Product Specification
95