MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 101

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
5.3.4
Note:
5.3.4.1
5.3.4.2
September 2007
Order Number: 318146-001
FB-DIMM Memory Events
Intel
correctable errors and detect uncorrectable errors. For either type of error, an SMI is
generated to the processor so that the EFI BIOS code can take the appropriate actions.
On the MPCBL0050, such actions include detecting the error and sending a memory
error event message to the IPMC firmware over the KCS interface. IPMC also logs
information events at board boot. These events provide information on memory
configuration detected by BIOS.
For details on memory detection and correction functionality, please refer to Intel
5000P data sheet available at www.intel.com.
Correctable Errors
MCH provides detection and correction of any x4 or x8 DRAM device failure. When an
error is detected, the chipset sends an SMI to BIOS. Then BIOS is responsible for
sending an event to the IPMC. DIMM information is also sent to the IPMC as part of the
event.
For each error occurence, the counter is incremented. To disregard intermittent errors,
the counters are decremented by one every 6 days.
Logging Threshold
The system detects, corrects, and logs correctable errors as long as these errors occur
infrequently (the system should continue to operate without a problem). Occasionally,
correctable errors are caused by the persistent failure of a single component. Although
these errors are correctable, continual calls to the error logger can affect system
performance, preventing further useful work.
For this reason, the system counts correctable errors and disables reporting if errors
occur too frequently. Error correction remains enabled, but calls to the error handler
are disabled. This allows the system to continue running despite a persistent
correctable failure.
• FRB-3 timeout - The FRB-3 algorithm is used to detect whether the boot strap
• Processor configuration error - EFI BIOS detected processor configuration error
• Processor presence - Indicates if the processor is present in the socket.
• Processor disabled
• PROCHOT - Indicates if the processor has entered automatic thermal throttling
processor is healthy and can run the EFI BIOS. The default FRB-3 timer is 10
seconds. The assumed initial condition is that both processors are enabled. The
basic algorithm is followed on each power up or system reset:
mode due to high CPU die temperature.
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— At power up/reset, the IPMC starts an internal FRB-3 timer.
— In a good system, the EFI BIOS issues the IPMI Set Watchdog Timer (WDT #1)
— In a failing system, the EFI does not issue the IPMI Set WDT command to the
— The IPMC logs an FRB-3 failure event against the failing processor sensor, logs
5000P MCH provides extensive logic built into the hardware to detect and correct
command with the “timer use” byte configured for the EFI BIOS. When the
IPMC receives this command, the IPMC starts the IPMI Watchdog Timer, and
then stops the internal FRB3 timer. At this point, the FRB-2 phase starts.
IPMC, and the IPMC FRB-3 timer expires.
a processor disable event against that processor sensor, then causes the
payload power to reset.
Intel NetStructure
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MPCBL0050 Single Board Computer
Technical Product Specification
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