MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 103

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.4
September 2007
Order Number: 318146-001
Critical Interrupt
MCH has build in capability to detect errors on the PCI and FSB interfaces. In case of
the errors detection BIOS SMI code will be executed and log appropriate events to SEL.
IPMB Link Sensor
The MPCBL0050 provides two IPMB links to increase communication reliability with the
shelf manager and other IPM devices on the IPMB bus. These IPMB links work together
for increased throughput where both buses are actively used for communication at any
point. A request might be received over IPMB Bus A, and the response is sent over
IPMB Bus B. Any requests that time out are retried on the redundant IPMB bus. In the
event of any link state changes, the events are written to the SEL. The IPMC monitors
the bus for any link failure and isolates itself from the bus if it detects that it is causing
errors on the bus. Events are sent to signify the failure of a bus or, conversely, the
recovery of a bus.
FRU Hot Swap
The Hot Swap event message conveys the current state of the FRU, the previous state,
and a cause of the state change as can be determined by the IPMC. Refer to the PICMG
3.0 specifications for further details on the hot swap state.
Ethernet Link Status
The IPMC firmware monitors the Ethernet link status (present/absent) of all available
ports on the SBC (two Base interface, four Fabric interface). One sensor is provided for
each of the six Ethernet links. Events are generated by the IPMC firmware when the
link status of the ports change.
Power Feeds, Power Supply, and Fuses
Power Feeds A and B, fuses on power feeds, as well as power good signals from all
onboard voltage converters monitored. In case of failure appropriate events are logged
to SEL.
IPMC Watchdog Timer Reset
As per PICMG 3.0 requirements (section 3.2.4.6.3), the MPCBL0050 provides a
watchdog timer that can reset the IPMC if the firmware hangs. After a reset, when
IPMC restarts, an event is generated indicating that the IPMC was reset due to
watchdog timer expiration.
Field Replaceable Unit (FRU) Information
The IPMC provides Field Replaceable Unit (FRU) information for the base board it
manages and major replaceable modules on the SBC, such as the RTM. FRU
information contained in the SBC includes data to describe the SBC as per the PICMG
3.0 Specification. Additional multirecords are provided to enable:
Inventory information on the MPCBL0050 is divided into different areas that are written
to at manufacturing time. Some information may be written by the BIOS during
initialization, which are identified where necessary.
• the BIOS to write CPU information and BIOS version number to FRU data correctly;
• customers to write their custom inventory information that is not part of any
inventory data provided by the MPCBL0050.
Intel NetStructure
®
MPCBL0050 Single Board Computer
Technical Product Specification
103