MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 88

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel NetStructure
Technical Product Specification
88
Table 28.
Sensor Name
CPU 1
ThermCtrl
CPU 2
ThermCtrl
CPU 1 VRD Hot
CPU 2 VRD Hot
CPU Config
Error
FI1 Junc TEMP
FI2 Junc TEMP
CPU1 PCBT
TEMP
®
IPMC hardware sensor and events (Sheet 15 of 18)
96h
97h
98h
99h
9Ah
9Ch
9Dh
9Eh
Sens
No.
MPCBL0050 Single Board Computer
or
Temp
01h
Temp
01h
Temp
01h
Temp
01h
Processor
07h
Temp
01h
Temp
01h
Temp
01h
Sensor
Type
Discrete
07h
Discrete
07h
Discrete
07h
Discrete
07h
Generic
03h
THreshold
01h
THreshold
01h
THreshold
01h
Reading
Event /
Type
00h
01h
00h
01h
00h
01h
00h
01h
01h
R,T
R,T
R,T
Offset
Event
[3:0]
ED1
Order Number: 318146-001
–
FFh
–
FFh
-
FFh
-
FFh
FFh
Byte
September 2007
2
Event Data
–
FFh
–
FFh
-
FFh
-
FFh
FFh
Byte
3
C
C
C
D
D
D
[u,l][nr,c,nc]
[u,l][nr,c,nc]
[u,l][nr,c,nc]
Transitioned to OK
Transitioned to Non-Critical
from OK
Percentage of time a
processor has been throttling
over the last 1.46 seconds
was larger than 0% and
previous state was
"Transitioned to OK".
Transitioned to OK
Transitioned to Non-Critical
from OK
Transitioned to OK
Transitioned to Non-Critical
from OK
Transitioned to OK
Transitioned to Non-Critical
from OK
State Asserted:
Logged by BIOS after
detecting improper CPU
configuration.
Event
MPCBL0050—Hardware Management
As & De
As & De
As & De
As & De
As & De
Assert
Events
As &De
As &De
As &De
assert
/ De-
–
–
-
-
Readab
Value /
–
–
-
-
Discrete
Analog
Analog
Analog
Offsets
le
M
M
A
A
A
A
A
A
–
–
–
–
X
X
X
N/A
N/A
N/A
N/A
N/A
0.5
0.5
0.5