MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 123

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
Figure 31.
5.12.3
5.12.4
September 2007
Order Number: 318146-001
Payload reset state diagram
Front Panel Payload Reset
The Reset button is a momentary contact button on the front panel. Its signal is routed
through the front panel connector to the IPMC, which monitors and de-bounces it. The
signal must be stable for at least 50 ms before a state change is recognized. The Front
Panel reset is mapped to generate a hard reset to the payload.
IPMI Commanded Reset
The IPMI Chassis Control command is supported and can be used to generate a hard
reset to the payload.
The Intel OEM Set Processor State command, which is used by the EFI BIOS during
POST, also generates a hard reset when used to disable a processor as part of the Fault
Resilient Booting (FRB) algorithm.
The PICMG FRU Control command can be used to generate either a hard or soft reset to
the payload.
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Intel NetStructure
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MPCBL0050 Single Board Computer
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Technical Product Specification
Hard Reset
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